1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which has a planarly dispersed charge storing means (for example, in a MONOS type or an MNOS type, charge traps in a nitride film, charge traps near the interface between a top insulating film and the nitride film, small particle conductors, etc.) in a gate insulating film between a channel forming region and a gate electrode in a memory transistor and is operated to electrically inject a charge (electrons or holes) into the charge storing means to store the same therein and to extract the same therefrom and a method of operating (writing or erasing) the device.
2. Description of the Related Art
In an information society, or high-speed, broadband network society, there is a great demand for large capacity file memories and memories for audio and video applications. Currently, in large capacity memory systems for storage of 1 GB (gigabytes) of data or more, use is made of disk memory systems employing disk storage media such as hard disks and optical disks. In recent years, studies have been actively performed trying to replace the disk media with nonvolatile semiconductor memories in this large market. Furthermore, mobile information terminals, which are capable of connecting to networks and expected to offer a large market in the future, are demanding removable storage media of small size and high reliability, and the nonvolatile semiconductor memory is the first candidate.
Although nonvolatile semiconductor memories suit the trend of small sized and light weighted hardware, presently, their storage capacities are still not sufficient, and semiconductor memories (flash memories) of capacities above 1 GB (gigabytes) and capable of erasure at one time have not been realized, yet. In addition to insufficient storage capacity, the reduction of cost per bit for the nonvolatile semiconductor memories is still not adequate compared with disk memories. In order to solve these problems, it is important to increase the integration degree of the nonvolatile semiconductor memories.
Along with the spread of broadband information networks, write speeds equivalent to the transmission rates of networks (for example, a carrier frequency of 100 MHZ) are being demanded even for nonvolatile semiconductor memories. This is because of the anticipation of development of information delivery employing a high-speed network in the near future. To realize high-speed downloads from networks, even nonvolatile semiconductor memories require write speed improvements of one or more orders of magnitude higher than the write speed of conventional FG-NAND type flash memories at 200 xcexcs.
As nonvolatile semiconductor memories, in addition to the floating gate (FG) types wherein the charge storing means (floating gate) for holding the charge is planarly formed, there are known MONOS (metal-oxide-nitride-oxide semiconductor) types wherein the charge storing means are planarly dispersed.
In an MONOS type nonvolatile semiconductor memory, since the carrier traps in the nitride film [SixNy (0 less than x less than 1, 0 less than y less than 1)] or on the interface between the top oxide film and the nitride film, which are the main charge-retaining bodies, are spatially (that is, in the planar direction and thickness direction) dispersed, the charge retention characteristic depends on not only the thickness of a tunnel insulating film (bottom insulating film), but also on the energy and spatial distribution of the charges captured by the carrier traps in the SixNy film.
When a leakage current path is locally generated in the tunnel insulating film, in an FG type, a large amount of charge easily leaks out through the leakage path and the charge retention characteristic declines. On the other hand, in an MONOS type, since the charge storing means are spatially dispersed, only the charges near the leakage path will locally leak from it, therefore the charge retention characteristic of the entire memory device will not decline much. As a result, in a MONOS type, the disadvantage of the degradation of the charge retention characteristic due to the reduction in thickness of the tunnel insulating film is not so serious as in an FG type.
In addition, in order to realize a high-speed and high capacity nonvolatile semiconductor memory, scaling of its gate length is indispensable, and for this, scaling of the thickness of a tunnel insulating film is required. In an FG type, due to the degradation of the above charge retaining characteristics, scaling of the thickness of a tunnel insulating film is difficult, making a simple gate length scaling difficult. In contrast, in a MONOS type, the thickness of a tunnel insulating film can be made thin, and the gate length can be further miniaturized by that extent easily. That is, a MONOS type is superior to an FG type in scaling of the tunnel insulating film in a miniaturized memory transistor with an extremely small gate length.
To realize a miniaturized memory cell in a MONOS type nonvolatile semiconductor memory, it is important to improve the disturbance characteristic. Therefore, it is necessary to set the tunnel insulating film thicker than the normal thickness of 1.6 nm to 2.0 nm. When the tunnel insulating film is formed relatively thick, the write speed is in the range of 0.1 to 10 ms, which is still not sufficient.
In other words, in a conventional MONOS type nonvolatile semiconductor memory etc., to fully satisfy the requirements of reliability (for example, data retention, read disturbance, data rewrite, etc.), the write speed is limited to 100 xcexcs.
A high speed is possible if the write speed alone is considered, but sufficiently high reliability and low voltage cannot be achieved. For example, a source-side injection type MONOS transistor has been reported wherein the channel hot electrons (CHE) are injected from the source side (IEEE Electron Device Letter, 19, 1998, p. 153). In this source-side injection type MONOS transistor, in addition to the high operation voltages of 12V for write operations and 14V for erasure operations, the read disturbance, data rewrite, and other facets of reliability are not sufficient.
On the other hand, taking note of the fact that it is possible to inject a charge into part of the dispersed charge traps area by the conventional CHE injection method, recently, it has been reported that by independently writing binary data into the source and drain side of a charge storing means, it is possible to record 2 bits of data in one memory cell. For example, Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-523, considers that by changing the direction of the voltage applied between the source and drain to write 2 bits of data by injecting CHE and, when reading data, applying a specified voltage with a direction reversed to that for writing, i.e., the so-called xe2x80x9creverse readxe2x80x9d method, correct reading of the 2 bits of data is possible even if the write time is short and the amount of the stored charge is small. Erasure is achieved by injecting holes by using a hand-to-hand tunnel current.
By using this technique, it becomes possible to increase the write speed and largely reduce the cost per bit.
However, in a CHE injection type MONOS type nonvolatile semiconductor memory of the related art, since electrons are accelerated in the channel to produce high energy electrons (hot electrons), it is necessary to apply a voltage larger than the 3.2 eV energy barrier of the oxide film, in practice a voltage of about 4.5V, between the source and drain. It is difficult to decrease this source-drain voltage. As a result, in a write operation, the punch-through effect becomes a restriction and good scaling of the gate length is difficult.
In addition, a write current of a few hundred xcexcA is needed, and as a result, there is another problem that it is impossible to write in parallel a large number of memory cells simultaneously.
Moreover, by a CHE injection method, because the write operation is performed with a current flowing in the channel of a memory transistor, it is impossible to simultaneously write at the source side and the drain side for the purpose of the aforesaid 2-bit data storage.
An object of the present invention is to provide a MONOS type or other nonvolatile semiconductor memory device, which basically operates by storing a charge in a planarly dispersed charge storing means such as a carrier trap, capable of write at a high speed with an extremely low current while suppressing the punch-through effect and wherein the scaling of the gate length and the thickness of the gate insulating film is good, and a method of operating (writing and erasing) the device.
According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a substrate, a channel forming region comprised of a first conductivity type semiconductor and formed in the substrate, a first and a second impurity regions comprised of a second conductivity type semiconductor and formed in the substrate and sandwiching the channel forming region between them, acting as a source and a drain in operation, a gate insulating film provided on the channel forming region, a gate electrode provided on the gate insulating film, and a charge storing means which is formed in the gate insulating film and dispersed in the plane facing the channel forming region and in the direction of thickness and is injected with hot holes at the time of operation from the first or the second impurity regions.
Preferably, the hot holes are those caused by a band-to-band tunnel current.
In the present invention, the number of recorded bits per cell may be either 2 bits per cell or 1 bit per cell.
In the former case, the gate insulating film may comprise a first region into which hot holes are injected from the first impurity region, a second region into which hot holes are injected from the second impurity region, and a third region between the first and second regions and not injected by hot holes.
Further, the charge storing means may be formed in the first and second regions, and the region of distribution of the charge storing means is spatially separated by the third region. In the case of a MONOS type, the first and second regions are stacked film structures comprised of a number of films stacked together, and the third region is a single layer of a dielectric.
Furthermore, preferably, the gate electrodes formed on the first and second regions and the gate electrode formed on the third region are spatially separated from each other. Alternatively, the nonvolatile semiconductor memory device further comprises a first control gate at the outer side of the first region and a second control gate at the outer side of the second region which are spatially separated from the gate electrodes on the first, second and third regions.
When the gate electrodes formed on the first and second regions and the gate electrode formed on the third region are spatially separated from each other, two channel forming regions of two memory transistors and a channel forming region of a select transistor in between are in connection with each other in series.
In the case of storing one bit per cell, preferably, a memory transistor comprising the channel forming region, the first and second impurity regions, the gate insulating film and the gate electrodes has a gate length of no more than the gate length when the regions retaining hot holes from the first and second impurity regions are merged or partially merged in the gate insulating film when hot holes are injected from both the first and second impurity regions.
Further, in the present invention, preferably, a plurality of memory transistors each including the channel forming region, the first and second impurity regions, the gate insulating film and the gate electrodes are arranged in both a word direction and a bit direction. The nonvolatile semiconductor memory device further comprises a plurality of word lines for connecting the gate electrodes in the word direction, and word drive circuits connected to the plurality of word lines for applying a negative voltage to selected word lines to which memory transistors to be operated are connected, and a positive voltage to nonselected word lines to which memory transistors to be operated are not connected.
In each of the plurality of memory transistors, a threshold voltage in a write state is lower than that in an erasure state. In addition, the first conductivity type is a p-type, and the second conductivity type is an n-type.
In the present nonvolatile semiconductor memory device, a separated source line type, virtual grounding type, or other NOR type cell array structure wherein a common line connected to the first impurity region (for example, the drain impurity region) and a common line connected to the second impurity region (for example, the source impurity region) can be controlled independently is preferable.
In a separated source line type, the common line connected to the first impurity region is referred to as the first common line, while that connected to the second impurity region is referred to as the second common line.
In this case, the first and second common lines may have a hierarchical structure. In a so-called AND type cell array, memory transistors are connected in parallel to the first and the second sub-lines that are used as the inner interconnections in a memory block.
According to the second aspect of the present invention, there is provided a method of operating a nonvolatile semiconductor memory device comprising a substrate, a channel forming region comprised of a first conductivity type semiconductor and formed in the substrate, a first and a second impurity region comprised of a second conductivity type semiconductor and formed in the substrate and sandwiching the channel forming region between them, acting as a source and a drain in operation, a gate insulating film provided on the channel forming region, a gate electrode provided on the gate insulating film, and a charge storing means which is formed in the gate insulating film and dispersed in the plane facing the channel forming region and in the direction of thickness and is injected with hot holes at the time of operation from the first or the second impurity regions. The method comprises a step of injecting hot holes into the charge storing means from the first or second impurity region when writing data to the device.
Preferably, the hot holes are those caused by a band-to-band tunnel current.
The operation methods are different for storing two bits in one cell and storing one bit in one cell.
In the former case, preferably, in a write operation, the method of operating a nonvolatile semiconductor memory comprises steps of injecting hot holes into the first region of the gate insulating film from the first impurity region, and injecting hot holes from the second impurity region into the second region separated from the first region in the gate insulating film independently from the injection of hot holes to the first region.
In the latter case, in the method of operating a nonvolatile semiconductor memory device, the region retaining hot holes injected from the first impurity region is merged or partially merged in the gate insulating film with the region retaining hot holes injected from the second impurity region. Specifically, the gate length of a memory transistor including the channel forming region, the first and second impurity regions, the gate insulating film, and the gate electrodes is no more than the gate length when the two regions retaining hot holes are merged or partially merged in the gate insulating film.
In the present invention, even when the first and second regions in one cell are separated from those in other cells in the word direction (separated source line NOR type) or the first and second regions are shred by cells in the word direction (virtual grounding type), if the first gate electrode on the first region and the second gate electrode on the second region are separated, memory cells connected to the same word line can be written simultaneously within one operation cycle.
That is, in a write operation of a nonvolatile semiconductor memory device having a memory cell array comprised of a plurality of memory transistors each including the channel forming region, the first and second impurity regions, the gate insulating film and the gate electrodes and arranged in both a word direction and bit direction, wherein the gate electrodes are commonly connected through the word lines for every certain number of memory transistors in a word direction, the method for operation of the memory cell array comprises steps of applying a specified voltage to all of the first and second impurity regions corresponding to the first and second regions into which hot holes are injected for all memory transistors connected to the same word line, setting the first and second impurity regions corresponding to the first and second regions not injected with hot holes to an electrically floating state, applying a predetermined write voltage equal to a difference between voltages applied to the first and second impurity regions on the same word line, and writing all memory transistors connected to the same word line in parallel in one operation.
Further, in the present invention, the method of operating a nonvolatile semiconductor memory comprises a step of applying a predetermined write voltage between the first or second impurity regions and the gate electrodes when writing data to the device. For example, in a write operation of a nonvolatile semiconductor memory device having a memory cell array comprised of a plurality of memory transistors each including the channel forming region, the first and second impurity regions, the gate. insulating film and the gate electrodes and arranged in both a word direction and bit direction, wherein the gate electrodes are commonly connected through the word lines for every certain number of memory transistors in a word direction, the method comprises steps of applying a negative voltage to the selected word lines to which memory transistors to be operated are connected, and applying a positive voltage to the nonselected word lines to which memory transistors to be operated are not connected.
Preferably, the method of operating a nonvolatile semiconductor memory device comprises a step of applying the same voltage to the first and second impurity regions when writing data to the device. This method of applying voltages can be used in both operations of writing 2 bits per cell and 1 bit per cell, but it is especially preferable in the latter case because it increases the injection efficiency of hot holes. Note that when injecting hot holes from one side, the first or second impurity region on the side not injecting hot holes needs to be set open.
In addition, for a nonvolatile semiconductor memory device having a memory cell array comprised of a plurality of memory transistors each including said channel forming region, said first and second impurity regions, said gate insulating film and said gate electrodes and arranged in both a word direction and bit direction, wherein the first impurity regions are commonly connected through said first common lines and the second impurity regions are commonly connected through said second common lines for every certain number of memory transistors in a bit direction, the method in a writing operation for the memory cell array comprises steps of applying a positive voltage to the first and second common lines to which memory transistors to be operated are connected; and applying a voltage of 0V to the first and second common lines to which memory transistors to be operated are not connected.
The method of operating a nonvolatile semiconductor memory device comprises in an erasure operation a step of injecting electrons from the entire channel to the charge storing means into which hot holes are injected from said first or second impurity region by utilizing the direct tunnel effect or the FN tunnel effect.
The present nonvolatile semiconductor memory device and the method for operating the same are suitable for devices where the charge storing means is formed and dispersed in a plane facing the channel forming region and in the thickness direction such as the MONOS type, small particle type having so-called nanocrystals or other small particle conductors, etc.
In the method of operating a nonvolatile semiconductor memory device according to the present invention, when the conductivity type of the channel forming region of the memory transistor is n-type, a positive voltage of for example 5.0 to 6.0 V is applied to the first and second common lines (the first and second impurity regions) to which memory transistors to be operated are connected. Further, a negative voltage of for example xe2x88x926.5 to xe2x88x925.0V is applied to the selected word lines (gate electrodes) to which memory transistors to be operated are connected. On the other hand, a positive voltage of for example 0V to 5V is applied to the other nonselected word lines, and a voltage of 0V is applied to the other nonselected first, second common lines and substrate.
By optimizing the concentrations of the first and second impurity regions, surfaces of the first and second impurity regions are in deep depleted state, and the energy bands in this inversion layer bend sharply. Due to the band-to-band tunnel effect, electrons tunnel from the valence band and the conduction band, and flow to the first and second impurity region. As a result, holes occur, and part of them are accelerated by the electric field and become hot electrons. While the high energy charges (hot holes) generated in the first and second impurity regions maintain their moments (magnitude and direction), without little energy loss, they are injected into the charge storing means (carrier traps) quickly and at a high efficiency. Although the charge injection areas from the source and drain regions are both localized, if the gate length is for example less than 100 nm, in the plane of distribution of the charge storing means, the charge injection area of the first impurity region and the charge injection area of the second impurity region are at least partially merged near the center, so the charge is injected into substantially the entire area. Consequently, the threshold voltage of the memory transistor is largely decreased. Although the hole current itself is small (the substrate current is 2 nA per cell), as described here, because the charge is injected into substantially the entire region of the plane of distribution of the charge storing means, the write time for obtaining a necessary change of the threshold voltage is, for example, less than 20 xcexcs or shortened by more than one order of magnitude when compared with a conventional memory cell that is able to be written in parallel.
On the other hand, as the most suitable memory transistor structure for writing 2 bits in one cell, for example, the gate insulating film including the charge storing means (carrier traps) is split in the channel direction into first and second regions located at the two sides of the gate insulating film and the third region between them is made of an insulating film of a single material not containing a charge storing means. The third region at the center functions as a MOS type control transistor.
In this structure, by controlling the threshold voltage of the MOS transistor within a certain range, reading can be performed with a constant current. In other words, when there is no MOS transistor, if the hot holes are over-injected and the threshold voltage of the memory transistor is largely decreased, the read current will fluctuate and much current will be wasted. However, in the present invention, because of the presence of the MOS transistor, if the threshold voltage of the memory transistor largely decreases and the read current starts to increase, the MOS transistor cuts off and functions as a limiter. As a result, in such a memory cell, the upper limit of the read current can be controlled by the threshold voltage of the MOS transistor and there is no unnecessary current consumption.
In addition, when erasing data, for example, under the condition that the first or the second impurity region and the substrate are set to 0V, a positive voltage is applied to the word lines, and electrons are injected into the charge storing means from the entire channel by using the direct tunnel effect or the FN tunnel effect. As a result, the threshold voltage rises leading to an erasure state. By this erasure method, it is possible to erase a block simultaneously.